The CMOS inverter in Figure 16.21 is biased at VDD = 3.3 V. Let Kn = Kp , VTN = 0.5 V, and VTP = -0.5 V. (a) Determine the two values of vI and the corresponding values of vO for which (dvO/dvI) = -1 on the voltage transfer characteristics. (b) Find the noise margins. Figure 16.21 CMOS inverter
Determine the noise margins of a CMOS inverter biased at VDD = 3.3 V with (W/L)n = 2 and (W/L)p = 5. Assume VTN = 0.4 V and VTP = -0.4 V. (b) Repeat part (a) for (W/L)n = 4 and (W/L)p = 12.
In the circuit shown below, the transistor has a b of 200. what is the dc voltage at the collector? Replacing the BJT with one of the hybrid-p models (neglecting r0), draw the equivalent circuit of the amplifier. Find the input resistance Rib and Rin and the overall voltage gain (vo/vsig). For an output signal of 0.4V, what value of vsig and vb are required.