If Pseudo-NMOS techniques are used to build a 2-input NAND gate with W/Lp = 2.3 and W/Ln = 28.9, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 uA/V2, k'p = 60 uA/V2
If Pseudo-NMOS techniques are used to build a 3-input NOR gate with W/Lp = 3.6 and W/Ln = 16.3, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 μA/V^2, k'p = 60 μA/V^2.
For the amplifier in Fig. 7.10, let VDD = 2 V, RD = 15 kohm, Vt = 0.5 V, k'n = 0.4 mA/V2, W/L = 12.5, VGS = 0.7 V, and lambda = 0. (a) Find the dc current ID and the dc voltage VDS. (b) Find gm. (c) Find the voltage gain. (d) If vgs = 0.015 sin wt volts, find Vds assuming that the small-signal approximation holds. What are the minimum and maximum values of vDS? (e) Use Eq. (7.28) to determine the various components of iD. Using the identity sin2 wt = 1/2 - 1/2 cos 2wt determine the second-harmonic distortion defined as the ratio of the component of iD of frequency 2w to the component of iD of frequency w, multiplied by 100.