The enhancement-type MOS transistors have the following parameters: VDD = 5 V |VT0| = 1.0 V for both nMOS and pMOS transistor lambda = 0.0 V-1 upCox = 20 uA/V2 unCox = 50 uA/V2 For a CMOS complex gate OAI432 with (W/L)p = 30 and (W/L)n = 40, (a) Calculate the W/L sizes of an equivalent inverter with the weakest pull-down and pull-up. Such an inverter can be used to calculate worst-case pullup and pull-down delays, with proper incorporation of parasitic capacitances at internal nodes into the total load capacitance. In this problem, you are asked to calculate only (W/L)worse-case for both p-channel and n-channel MOSFETs by neglecting the parasitic capacitances.