The schematic diagram of a MOSFET bias voltage generation circuit is shown below. The gate lengths of both transistors are the same and equal to the minimum length for this technology L1 = L2 = Lmin and the magnitude of the threshold voltage is |VT| = 1 V. Channel length modulation can be neglected and the same process is used for both transistors. Please answer the following questions: 1. derive an expression for the output voltage Vo in terms of the supply and threshold voltages of the transistors and the ratio of the channel widths. Clearly state all assumptions. 2. hence or otherwise, design a MOSFET bias voltage generation circuit to output 3 V, where all transistor widths are expressed as integral multiples of the minimum length W1 = N1Lmin ? where N1 E N. Verify all assumptions.
A schematic diagram of a potential divider circuit is shown below. If the gate lengths of both transistors are the same, establish the ratio of the gate widths required to generate a Vo = 3V, where VDD = 12V. Channel length modulation can be neglected and the magnitude of both threshold voltages are both |VT| = 1V. Verify all assumptions.