Analyze the FET circuit shown when VDD = 14V, k = 400 uA/V^2, R1 = 10Mohm, R2 = 35Mohm, RD = 4kohm, VT = -1.5 V. What should be the range of the DC source, VDD, be to keep the PMOS in the saturation region?
The below truth table is given for a Boolean function f(x1, x2, x3). Implement f with a CMOS circuit having a Pull Up Network consisting of PMOS transistors and a Pull Down Network consisting of NMOS transistors. Sketch the circuit.
The p-channel MOSFET circuit with terminal voltages is shown in Figure 3. Answer the following question by using device data given. i. Label and indicate value for the source and the drain terminals. (4 marks) ii. Identify in which region the transistor is operating. Prove your answer by showing the calculation. iii. Find the drain current - ID
2. The p-channel MOSFET circuit with terminal voltages is shown in Figure 9. Answer the following questions by using given device data. (a) Label and indicate value for the source and the drain terminals. (4 marks) (b) Identify in which region the transistor is operating. Prove your answer by showing the calculation. (6 marks) (c) Calculate the drain current, - ID, (4 marks) (d) Determine the new operating region when the applied source, VS is change to 4V. Assume the source-bulk voltage, VSB is not zero. (6 marks)