1. Give a complementary p-channel network to the n-channel network shown in Figure 1. 2. What is the logic function realized by the gate shown in Figure 1? 3. Design a CMOS gate that realizes the function, out = x1 + x2(x3 + x2). Simplify the gate.
Find Traditional CMOS realizations to the following truth table using Karnaugh map techniques. Find realizations based on grouping the 1 s. What is the worst-case equivalent resistor during a "0" to "1" transition of the output? Assume all transistors are 6um/0.6um. You may assume the inputs and their complements are available. Note that "d" designates a "don't care" situation. Use, Kn' = 190 uA/V2, VTN = 0.7 V for NMOS and Kp' = 50 uA/V2, VTP = -0.8 V for PMOS transistors, VDD = 3.3 V. 2. Repeat problem 1 but base your design on grouping "0"s. Design the W/L ratios of each MOSFET so that the gate will have the same response of a CMOS inverter whose n-channel pull down transistor has WN/LN = 8um/2um. Use channel length of 2 um for each transistor.