7.1 For the MOS amplifier of Fig. 7.2(a) with VDD = 3 V, Vt = 0.5 V, kn = 10 mA/V2, and RD = 15 kΩ, determine the coordinates of the active-region segment (AB) of the VTC [Fig. 7.2(b)]. (a) (b) Figure 7.2 (a) An NMOS amplifier and (b) its VTC. ANSWERS GIVEN IN THE BOOK: A: (0.5 V, 3 V) B: (0.69 V, 0.19 V)
The shown circuit is called the cascode configuration, where two transistors are cascaded. The parameters for each transistor in the figure are β1 = 80, β2 = 50 and VBE(on) = 0.7 V. a) Assume both transistors are active, calculate all the currents in the circuit. b) Verify that the assumption in part (a) is correct c) Calculate the ratio Ix/IB1 d) Express Ix/IB1 in in terms of β1 and β2.
A three-input CMOS NAND gate is designed as shown below. Assume that VDD=1.2 V, K'n = 90 uA/V2, Vtn = 0.4 V, K'p = 50 uA/V2, and Vtp=-0.5 V in the 100nm technology node. Determine the width of NMOS and PMOS transistors in this NAND gate, such that the worst case delay becomes equivalent to a referenced inverter with Wn=1um and Wp=2um. For the device sizes found in part (a), determine the switching threshold voltage, VM, when all inputs are tied together. Find the maximum IDD current for this NAND gate.