Consider the CMOS inverter, connected in resistive feedback, shown below. Model the transistors as having square-law behavior, such that ID1 = knW1/L1( VGS - VTHn)2(1+lambda*VDS) and ID2=kpW2/L2( VGS-VTHp)2(1+lambda*VDS). Also assume: kn=3kp, VTHN=-VTHP =VDD/3, that the devices have the same value of ? and that the nmos bulk is grounded, and pmos bulk is to VDD. Also assume the circuit is biased so that if Vin =Vin0+?Vin then when Vin =Vin0, Vout =Vin . Draw the complete small-signal model of this amplifier, showing each transistor's elements explicitly, assuming M1 and M2 are in saturation. Then, redraw a simplified small signal model (collapsing parallel resistances, capacitances and transconductances into single components and eliminating zero-value components), in this simplified model, also apply Millers' theorem to break RF into resistors to ground on input and output (leave voltage gain as an unknown variable Av ).
Draw the small-signal model for the circuit shown below, where M1 and M2 can be assume to operate in saturation mode and λ ≠ 0. Use the appropriate small signal parameter variables where necessary, e.g. you may use gm1 and gm2 to describe the transconductance for transistors M1 and M2, respectively. Also, derive an expression for the small-signal voltage gain.
Consider the CMOS inverter shown below, Model the transistors as having square-law behavior such that i) lD1 = 1/2knW1/L1(VGS-VTHn)2(1+lambda*VDS) ii) ID2 = 1/2kpW2/L2(VGS-VTHP)2(1+lambda*VDS) iii) kn = 3kp iv) VTHN = -VTHP = VDD/3 v) The devices have the same value of lambda vi) The NMOS bulk is grounded and PMOS bulk is to VDD vii) The circuit is biased so that if VIN = VIN+?VN, then when VIN = VIN0, VOUT = VIN. a) Choose W1/L1 relative to W2/L2 such that VIN = VOUT = VDD/2. b) Draw the complete small-signal model of this amplifier, assuming M1 and M2 are in saturation. Draw a simplified small signal model (collapse parallel resistances, capacitances and transconductances into single components and eliminate zero-value components).