For an NMOS differential pair with a common-mode voltage vCM applied, as shown in Fig. 7.2, let VDD = VSS= 2.5 V, Kn
7.2 For the PMOS differential amplifier shown in Fig. P 7.2 let Vtp = -0.8 V and kp'W/L = 3.5 mA/V2. Neglect channel-length modulation. Figure P7.2 (a) For vG1 = vG2 = 0 V, find VOV and VGS for each of Q1 and Q2. Also find vs, vD1, and vD2. (b) If the current source requires a minimum voltage of 0.5 V, find the input common-mode range.
Hand Calculation The shown circuit is called the cascode configuration, where two transistors are cascaded. The parameters for each transistor in the figure are B1 = 80, B2 = 50 and VBE(on) = 0.7 V. a) Assume both transistors are active, calculate all the currents in the circuit. b) Verify that the assumption in part (a) is correct c) Calculate the ratio Ix/IB1 d) Express Ix/IB1 in in terms of B1 and B2. Simulation Draw the circuit on LTSpice and create: a model for Q1 with IS = 1x10-15 A, and BF = 80 a model for Q2 with IS=1x10-15 A, and BF = 50 a) Verify the current values in part (a) in the hand calculations b) From the simulation results calculate Ix/IB1 and verify part (c) in the hand calculations c) Try different values for B1 and B2 and verify the expression obtained in part (d) in the hand calculations Notes: Homework submission is through the Moodle platform Submit a single compressed file containing a folder for each question containing : The hand calculations Screenshots showing the circuit and the simulation results for parts (a) (b) and (c) The schematic file (.asc) The netlist file (.net)
Consider the shown circuit and assume R = 2 kohm and: D1 and D2 have V = 0.7 V and a very large breakdown voltage DZ1, DZ2 are Zener diodes with V = 0.7 V and breakdown voltage of 6 V Hand Calculation a) Calculate Vo at: vI = -8 V vI = -5 V vI = 4 V vI = 9 V b) Fill in the table below, where the state of the diode could be: Forward (F), Reverse (R) or Breakdown (BR) c) Find the range of voltages for vI that make D1 forward biased and DZ1 in breakdown d) Find the range of voltages for vI that make D2 forward biased and DZ2 in breakdown e) Find the range of voltages for vI that make all diodes reverse biased f) Plot vI (on the x-axis) with vO (on the y-axis) for the range ?10 < vI < 10 g) Assume that vI(t) = 10sin(6pit)V, plot vO(t). Simulation Draw the circuit on LTSpice and note that: the model for D1, D2 is constant drop with Vfwd = 0.7 the model for DZ1, DZ2 is constant drop with Vfwd = 0.7 and a breakdown voltage Vrev = 6 a) Perform DC operating point simulation to verify the results in pan (a) in the hand calculations b) Perform DC sweep simulation to verify the plot in part (f) in the hand calculations c) Choose VI to be sinusoidal with VI(t) = 10sin(6pit) V, use transient simulation and plot 3 cycles of Vo and verify the plot in part (g) in the hand calculations