Figure 3-1 shows a MOSFET test circuit used to generate the curve shown below. The data was taken by varying vGS and measuring the MOSFET turn-on resistance rDS with an ohmmeter. MOSFET Turn on Resistance a) Using this data, determine values for the MOSFET parameters kn
The circuit shown in Figure 5-1 is a CMOS logic gate of some type. NOTE: Alternative symbols! a) Fill in the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] If 0 V represents a logic low, and +5 V represents a logic high, what is the logic gate function of this circuit? [2] c) Determine the output resistance ROUT of the CMOS gate of Figure 5-1 for each combination of inputs. [8] NOTE: ROUT is the Thevenin Resistance of the Gate. It is the total resistance connected between VDD and the output OR between the output and GROUND, depending on the state of the MOSFET switches. GIVEN : rDSn = 190 ohm and rDSp = 350 ohm d) If this gate exhibits a worst-case Low-to-High (tpLH) propagation delay of 60nsec when driving a given capacitive load, what would you expect the worst-case High-to-Low (tpHL) propagation delay to be?
For an n-channel MOSFET, when vDS is held constant and vGS is increased beyond the threshold voltage, iD : (a) increases (b) does not change (c) decreases (ii) The MOSFET has small-signal parameters: gm = 20mS r0 = 10 kohm The open circuit voltage gain, Av0, is (a) -66.0 V/V (b) -200 V/V (c) -49.6 V/V (iii) The AC input resistance, Ri, of the amplifier in question (ii) is: (a) infinite (b) 15.95 kohm (c) 1.140 kohm (iv) The AC output resistance, R0, of the amplifier in question (ii) is: (a) 3.3 kohm (b) infinite (c) 2.48 kohm (v) The DC bias current, ID, of the amplifier in question (ii) is: (a) 2 mA (b) 20 mA (c) 50 mA