For the MOSFET amplifier, given VDD = VSS = 9V, Rsig = 2Kohm, R3 = 10Kohm Assume R6 = 4.2Kohm, RD = 12Kohm and gm = 6.3ms determine the voltage gain Av (=vo/vsig ) in dB
In the circuit below (a) What value of R will give a current of 100 mA? (You may ignore the base current in your answer.) (b) What is the maximum value of Rload for which the source will continue to deliver 100 mA?
Transmission gate logic a. Determine the function E. b. What is the role of the pMOS transistor.
For the circuit in Figure 4, you can ignore body effect and channel length modulation. Equivalent resistance Req (W/L=1) of NMOS and PMOS transistors are Rn = 10 k and Rp = 25 k, respectively. (a) What function is implemented by this circuit? (b) Calculate the worst-case low-to-high propagation delay. Assume that all output capacitances are lumped together into a single load capacitance CL = 45fF. You may ignore all intermediate (internal) capacitances for this part. (c) Calculate the fastest high-to-low propagation delay. CL = 45fF. You may ignore all intermediate (internal) capacitances for this part. (d) What are the input patterns that give the worst-case tpHL and tpLH. State clearly what the initial input patterns are and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes for part (d).