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  • Electrical Engineering Archive: Questions from 2023-10-28

    Considering the CMOS inverter shown in the figure below, (W/L)n = 1/4, (W/L)p = 1, and VDD = 3.3 V. Find (1) expression of Δt = t2−t1, using the integral method, (2) if C = 40 fF, the value of Δt = t2−t1, using the average current method, and (3) based on the result obtained in (2), determine the duration of T and the switching power dissipated in the inverter.

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    Consider the amplifier circuit shown in the figure below. MOSFET channel length modulation can be neglected, VDD = 5 V, Vtn = 0.7 V, and kn = 1 mA/V2. Find VOV, ID, RD and RG to obtain voltage gain equal to −25 V/V and an input resistance of 0.5 MΩ. What is the maximum allowable input signal, vi? Tip: during small signal analysis you can assume that current through resistor RG is much smaller than gmvGS current and check if this is satisfied later. (Ans. 0.319 V; 50.7μA; 78.5kΩ; 13MΩ; 27mV)

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    Consider the MOSFET feedback amplifier shown in the Figure. The transistor parameters are VTN = 0.5 V, Kn = 0.5 mA/V2, and λ = 0. a. What is the topology of the feedback b. Using the topology method, determine the small-signal voltage gain Avf = vo/vi. c. Use the Test Method to verify your answer in (b)

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