For the following NMOS amplifier (with another NMOS used as a pull-up). The following parameters are for both M1 and M2 transistors: Vdd = 2.5v Vbs = 0 Vt0 = 0.5v lambda = 0.11v-1 W/L = 10 unCox = 200.0 uA/V2 a) For VIN equal to 1.25 V, what region is transistor M1 operating in? Find VOUT . b) For VIN equal to 2.0 V, what region is transistor M1 operating in? Find VOUT. c) Create a small signal model for this circuit. Find open circuit gain AV. d) For VIN equal to 1.25 V, Find the value for open circuit voltage gain, AV. Hint: Need values for gM1, gM2, rOM1, rOM2; combine two small signal models, one for each transistor, to find the final small signal model.
Implement a four input NAND and four input NOR in CMOS static style design. For the circuit(s) specify the W/L ratios of all transistors in terms of the ratios of n and p of the basic inverter, such that the worst case tPLH and tPHL are equal to those of the basic inverter.
Implement the equation X = ((A'+B') (C'+D'+E')+F')G' using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance?
a) Calculate the capacitance (in Cs) for the output node of Circuit B b) Calculate the capacitance (in Cs) for the output node of Circuit A c) Calculate the capacitance (in Cs) for the output node of Circuit C d) Calculate the capacitance (in Cs) for the output node of Circuit D e) Calculate the capacitance(in Cs) for the output node of Circuit G f) Calculate the capacitance (in Cs) for the node between nMOS transistors switched by inputA and inputB inG g) Calculate the capacitance (in Cs) for the node between pMOS transistors switched by inputA and inputB of Circuit D h) Calculate the capacitance (in Cs) for the node np1 (look at the figure) of Circuit G i) Calculate the capacitance (in Cs) for the node np2 (look at the figure) of Circuit G j) Calculate the capacitance (in Cs) for the node nn1 (look at the figure) of Circuit G