Consider the following common source amplifier with a current mirror load Assume the following process parameters: VDD = 3.3 V Vtn = ∣Vtp∣ = 0.5 V kn′ = 5 mA/V2 kp′ = 3.2 mA/V2 You are now told that IREF = 500 μA and (W/L)Q1 = 10, (W/L)Q2 = 10, (W/L)Q3 = 5. Assume all transistors are in saturation. Find the DC bias current, ID. (Ignore the Early effect). Find the transconductance of Q1, gm1. (Ignore the Early effect).
(a) What is the logic function implemented by the gate in Fig. P7.84? (b) Design the PMOS transistor network. Select the device sizes for both the NMOS and PMOS transistors to give a delay of approximately one-half the delay of the CMOS reference inverter. C is the same. (c) What is the equivalent W/L ratio of the NMOS switching network when all of the NMOS transistors are on? (d) Repeat for the PMOS network.
In the following current mirror determine: (a) the dimensions of M2 and M3 in order to have an output current of 40 μA if Iref is equal to 10 μA. (b) The effect on the current mirror if M3 dimensions are changed to 40/1 (μm/μm); (c) Determine the minimum output voltage that allows all the devices to work in saturation Suppose that (W/L)1 = 5/2 (μm/μm) and (W/L)4 = 5/1 (μm/μm) Data: VTN = 1 V; VTP = −0.7 V, μnCox = 110 μA/V2; μpCox = 50μA/V2; λp = 0.05 V−1; λN = 0.04 V−1
In the following current source (a different version of the regulated cascode) calculate Rout and Vout(min) when: a. M1 and M2 are in saturation. b. M1 is in triode and M2 is in saturation. Note: A is the gain of the amplifier. This question does not require numerical calculations, express your answer in MOSFET parameters (gm, rds, A, etc)