In this question, we will study the source follower cascaded by a CS stage. Neglect body effect and channel length modulation. (a) First we carry out a dc analysis on the CS stage. In the CS stage circuit shown in Figure 1, assume μnCox(W/L)1 = μpCox(W/L)2 = 1mA/V2, VTN = 0.7V, VTP = −1V, VDD = 2.5V. Calculate I1 and VOUT such that M1 operates in saturation with VGS1 = 0.8 V. What is VIN if M1 is at the edge of saturation? (b) Then we do small signal analysis on the CS stage. In the circuit shown in Figure 1, derive the small signal voltage gain Av = vout/vin. What is the maximum dc level of Vin for which M1 remains saturated? Express VIN by VDD, gate-source voltages and threshold voltages of M1 and M2. (c) To accommodate an input de level close to VDD, we further cascade it with a source follower as shown in Figure 2. Derive the small signal gain vout/vin. If VIN = VDD, what relationship between the gate-source voltages of M2 and M3 guarantees that M1 is saturated?
Assuming that transistors M1 is properly biased ( Vin has a proper DC component and a small-signal component) and M1 and M2 are operating in the saturation region, and capacitor C is large enough such that at the frequency of the input small signal it can be considered as a short circuit, find Find RL such that the magnitude of the small-signal gain of the circuit, namely, ∣Vout/Vin ∣ is 5 V/V. In the following circuit we have: VDD = 3 V (W/L)3 = (W/L)5 = (W/L)6 = 10 (W/L)4 = 40 (W/L)2 = 100 (W/L)1 = 25 R = 1 kΩ The technology parameters are: λ(NMOS) = λ(PMOS) = 0 V−1, γ = 0, VTH(NMOS) = ∣VTH(PMOS)∣ = 0.5 V, μnCox = 0.5 mA/V2, μpCox = 0.25 mA/V2.
The following figure contains a pass-gate logic network, assume long channel transistors. a. Determine the truth table for the circuit. What logic function does it implement? b. Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve a VOL = 0.3 V. Take VDD = 2.5v c. If the PMOS were removed, would the circuit still function correctly? Does the PMOS transistor serve any useful purpose? - NMOS VTo = 0.4 v, k′ = 100 μA/V2 - PMOS VTo = −0.4 v, k = 40 μA/V2