Obtain the steady-state voltages at the nodes of the following circuit. All capacitances are 0.1pF each, all transistors have W/L = 3, VDD = 1 , Vtn = 0.25 V, Vtp = −0.35 V, and L = 100 nm.
Please use VDD of 3.3V You can use minimum L = 400 nm in this circuit Use PFET3.3 and NFET3.3 1. Implement the circuit shown in the Figure 1. Provide the hand calculation for obtaining the IREF. The mirror currents must be close to the values shown.
Gilbert Cell: A typical MOS gilbert cell is shown below. It has variety of applications such as double-balanced mixer, four-quadrant multiplier, and variable gain amplifier. (a) Derive the complete expression for Vout as a function of VLO and VRF. Use the standard drain current equation shown below for all NMOS transistors. Assume there is no channel length modulation effect (r0 = ∞). Transistors M1 & M2 have width W1 and length L1, M3 - M6 have width W3 and length L3. (b) If both the VLO and VRF are small (small signal approximation), properly simplify the expression obtained in (a) to a 1st-order equation. What is the linearized conversion gain of the mixer k? Vout = k⋅ VRF ⋅ VLO (c) If μn = 425 cm2/Vs, tox = 100 Angstrom, εr,ox = 3.9, and εo = 8.85 × 10-12 F/m, Iss = 200uA, L1 = L1 = 1um, W1 = 2 * W3 = 100um, R = 1kΩ. Calculate the numerical value for the conversion gain in (b)?
1. Find the Input impedance of the following Amplifier 2. Comment on the pole frequency at the input
For the shown circuit (a) Calculate small-signal voltage gain. (b) Calculate output impedance. The biasing voltage is VB = 4 V and the transistor sizes are (W/L)1 = 16/1 and (W/L)2 = 4/1. Use the following parameters: Vdd = 5 V, kn = 100 μA/V 2 , kp = 50μA/V2 , Vthn = 0.6 V, Vthp = -0.8 V, λn = 0.02 V -1 , λp = 0.02 V -1 , γ = 0.
Consider the circuit in the schematic below. The channel lengths are all 2λ. The NMOS widths are 16λ and the PMOS widths are 35λ. a) (10 pts) What is the boolean function? b) (10 pts) Find the equivalent W/L ratios for the NMOS and PMOS transistors if you include all of the transistors. c) (10 pts) Now consider that B is switching with D and C low and A and E high. Find the equivalent W/L ratios for the NMOS and PMOS transistors and exclude the OFF transistors.
Distortion: For the PMOS differential pair with source degeneration shown below (μpCox = 30 μA/V2, Vto = -0.7 V, λ = 0 ): (The body of all transistors are connected to their own source) a) Calculate the rms input voltage that yields IM3 = 1% in the output voltage vo. b) Repeat part (a) for two identical cascaded stages such as the one shown below (take vo as the output of the second stage). Figure 8. PMOS differential pair with source degeneration
For a prototype OpAmp, given VDD = 8 V, -VSS = -8 V, and given gm2 = gm6 = gm7 = gm8 = 5mS, gmg = 1.2mS. VTN = 1.3 V, VTP = -1.0 V VGS1 = VGS2 = VGS5 = VGS6 = 2 V, VGS7 = VGS8 = 2.1 V, VSG10 = VSG11 = 1.7 V. Determine the minimum voltage for the common mode input
Consider Mirror Adder circuit below: (a) Size NMOS and PMOS devices in the circuit so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in an inverter. Assume that all the transistors in the circuit and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2 × WMIN. You can mention sizes in the figure itself. (b) How can you resize transistors from your solution in (a) to make the circuit faster? You are not allowed to increase the total area of your circuit.
The circuit below shows an MOS differential amplifier with the drain resistors RD implemented using diode-connected PMOS transistors, Q3 and 24. Let Q1 and Q2 be matched, and Q3 and 24 be matched. The transistor parameters are: µn Cox = 4.µpCox = 400 mA/V2, Vtn = |Vtpl = 0.5 V, VAn = IVApl = 60, (W/L)1,2 = 250, and (W/L)3.4 = 10. The power supplies are VDD = 6 V and Vss = -6 V. This amplifier is biased using a current sink with I = 250 µA, output resistance Rss = 25 kΩ, and the minimum voltage drop Vcs,min = 0.5 V across it. Choose all correct statements about (1) the DC output voltage Vo, (2) the highest common-mode voltage VCM,max (3) the minimum common-mode voltage VCM,min (4) the differential-mode gain Ad, and (5) the common-mode gain Vcm
1. What operating region is M1 in? 2. What is the value of ΔV for M1 and M2? 3. What range of V2 can be supported while keeping M2 in saturation? 4. Assuming M2 is in saturation, what is the value of I2 in relation to I1, W1, and W2? 5. What is the value of the output impedance, Z2, under the following conditions: a. λ = 0, M2 in saturation b. λ = 1/(10 V), M2 in saturation c. M2 in triode region (For M2, assume Vds ≪ ΔV ) VTHn = 0.5 V, VTHp = -0.5 V, μnCox = 50μA/V2, μpCox = 20μA/V 2 , λ = 0, γ = 0, L = 0.15μm, W1 = 15μm, W2 = 30μm, W3 = 75μm, All voltages must be in the range of 0 V to 1.3 V
Specifications: (1) Two NMOS transistors are matched: μnCox = 200μA/V2, Vtn = 2 V,λn = 0.01 V−1, Wn = 1μm, L = 0.2μm. Please short the BODY to the SOURCE. (2) ISS = 4 mA, RSS = 2kΩ, RD = 1.5kΩ, ΔRD = 0.2⋅RD, VDD = 10 V, and VB = 5 V. (3) The differential-mode AC sinusoidal signal, vd, has 200mV amplitude and 2kHz frequency. (4) The common-mode AC sinusoidal signal, vc, has 200mV amplitude and 0.4kHz frequency. (5) Note that the differential-mode gain, Ad = ∣vOP−vON//∣vd∣. (6) Note that the common-mode gain, Ac = ∣vOP−vON∣/∣vc∣. Design Estimations & Simulations: (a) Estimate the differential-mode gain, Ad, by hand-calculations (Hint: set λn to zero). (b) Verify the differential-mode gain by a .TRAN transient simulation (Hint: set vc to zero for your differential-mode simulation). (c) Estimate the common-mode gain, Ac, by hand-calculations (Hint: set λn to zero). (d) Verify the common-mode gain by a .TRAN transient simulation (Hint: set vd to zero for your common-mode simulation). (e) Find estimated CMRR in dB based on (a) and (c). (f) Find simulated CMRR in dB based on (b) and (d). (g) Run a .TRAN simulation to plot realistic waveforms of vIP, vIN, vOP and vON by simultaneously tuning on vd and vc.
All transistors are in the saturation region; the transconductances of M1, M2, M3 and M4 are gml1, gm2, gm3 and gm4, respectively; the output resistances of M1, M2, M3 and M4 are ro1, ro2, ro3, and ro4, respectively. Also, gm1 = gm2 and ro1 = r02 ≫ RD. The tail current source of this differential amplifier is implemented in the cascode structure (M3 and M4), and the load resistors have a very small amount of mismatch, ΔRD. Hint: the output impedance the current source should be the same as the output impedance of a cascode amplifier. (a) Derive the expression of the differential-mode gain, Ad = (v0+−vo−)/vd. (b) Derive the expression of the common-mode gain, Ac = ∣vo+−Vo−∣/∣vc∣. (c) Derive the expression of the common-mode rejection ratio, CMRR = ∣Ad∣/∣Ac∣, for this differential amplifier.