For the circuit shown below, let's assume M1 and M2 are operating in saturation mode, with a drain current of ID = 198 μA. We further assume that the transconductance for M1 is gm1 = 3.3 mS and for M2 it is gm2 = 3.9 mS. The channel-length modulation parameters for the two transistors are λ1 = 0.026 V-1 and λ2 = 0.017 V-1. What is the small-signal voltage gain of the circuit? Give your answer to 0 decimal place.
In the circuit of Fig. 1, VDD = 3 V and IREF = 100 μA. The input CM level applied to the gates of M1 and M2 is equal to 1.3 V. The device parameters are shown in table 2. You need to take source/ drain side diffusion into consideration and assume λ = γ = 0. All transistors are operated at saturation region. (40 pts) (a) Determine Vp. (b) Determine drain voltage of M3. (c) Determine IDS,M10 and ISD,M5. Figure 1 Table 2 Cox = 3.837×10-3 F/m2 For Nmos: Vth = 0.7 V2 ΦF = 0.9 V λ = 0.1 V-1 γ = 0.45 V1/2 For Pmos: Vth = -0.8 V 2ΦF = 0.8 V λ = 0.2 V-1 γ = 0.4 V1/2
Consider the circuit given in the following figure. Assume that all NMOS transistors have an equivalent ON resistance Rn and all PMOS transistors have an equivalent ON resistance Rp. a) Write the equation for high to low propagation delay (tpHL) at the output of 4-input NAND gate using Elmore delay model. b) Write the equation for low to high propagation delay (tpLH) at the output of 4-input NAND gate assuming all inputs switching from logic high to logic low.
For the n-channel MOSFET transistor we have the following information: tox = 2 nm L = 0.2 μm, W = 1 μm, Lov = 0.03 μm, Csb0 = Cdb0 = 2 fF V0 = 1 V, VSB = 0.1 V VDS = 0.9 V, ε0 = 3.45×10-11 F/m. Find all the internal capacitance values for this NMOS.
Design the CMOS cascode amplifier of Fig. 4.1 for a voltage gain of 200 and a power budget of 2 mW with VDD = 1.8 V. Assume (W/L)1 = … = (W/L)4 = 20/0.18 and λp = 2λn = 0.2 V-1. Determine the required dc levels of Vin and Vb3. For simplicity, assume Vb1 = Vb2 = 0.9 V.
Design a CMOS inverter, using LTSPICE, with the following specifications: VDD = 3 V, Ln = Lp = 10 um, and Wn = 20 um. Find the Wp to set the switching point to 0.50∗VDD. Measure the propagation delays (TPLH, TPHL). Use the given device models in the simulation: .MODEL NMOS NMOS LEVEL = 1 VTO = 0.7 KP = 110U LAMBDA = 0.04 GAMMA = 0.40 PHI = 0.7 .MODEL PMOS PMOS LEVEL = 1 VTO = -0.7 KP = 50∪ LAMBDA = 0.05 GAMMA = 0.57 PHI = 0.8 Submit a report (Lastname_Coursework1.pdf) comprising of schematic diagram, simulation setup. simulation results, and discussion on the effect of transistor sizes on the switching point and the propagation delays. Submit also the LTSPICE file (Lastname_Coursework.asc). Figure 11.5 Transfer characteristics of the inverter showing the switching point. Figure 10.9 Definition of delays and transition times.