What is the propagation delay for a falling edge in picoseconds for a 2 -input NOR gate in a 0.35μm CMOS process if the total capacitance on the output of this logic gate is 65.9fF ? Do NOT use the Elmore formula. Use: W/Lp = 12.2, W/Ln = 7.2, VDD = 3.3 V, VTN = 0.7 V, VTP = -0.7 V, k'n = 100 μA/V^2, k'p = 40 μA/V^2
For the CMOS Inverter operating at the point of interest shown, which of the following five equations appropriate for describing the input-output relationship. Use VDD = 5 V as a power supply value. MOSFET Parameters: Electrically-matched devices Kn = Kp = 50 μA/V2 VTN = |VTP| = 1 V λn = λp = 0 V-1
The MOSFET in this amplifier has VT = 2.0 and k = 100 mA/V2. Ignore any effects of the MOSFET output resistance Ro. a. Determine the DC values of ID, VG, VD. Answer check: VD = 2. 44 b. Verify the MOSFET is in saturation. c. Determine the MOSFET's transconductance. d. Determine the voltage gain of the amplifier. Answer: Av = -44 e. Recalculate the voltage gain if the amplifier is driving a 1 kΩ load resistance connected from Vo to ground. f. Calculate the input resistance of the amplifier looking into Vi. g. Suppose the MOSFET has an Early voltage VA = 50 V. Ignoring the effects of Ro on the DC properties of the amplifier, what will be the voltage gain including the small-signal effects of Ro along with the 1kΩ load resistor? Answer check: Av = -20
Given a CMOS inverter with the following operation and devices characteristics: pMOS transistor: W/L = 4; mobility = 120 cm2 /V*; threshold voltage = -0.6 V nMOS transistor: W/L = 1; mobility = 240 cm2 /V*s; threshold voltage = 0.6 V 240 nm process; gate oxide capacitance/unit area = 8.6 × 10-7 F/cm2, VDD = 2.4 V a. Calculate Beta, β, for each transistor? b. What modes/regions of operation are the transistors in when Vin = 0.2 V? c. Calculate the inverter rise and fall times given a load capacitance of 100 fF? d. Calculate the average propagation delay of the inverter? e. Draw the VTC curve with a VIL of 0.8 V and a VIH of 1.4 V? Label all significant points. f. Calculate the noise margin?
The NMOS and PMOS transistors have the following characteristics. The channel length is 350 nanometers. For NMOS: tox = 50 nm, Vtn = 0.25 V, un = 560 cm2/vsec, W = 700 nm, L = 350 nm For PMOS: tox = 50 nm, Vtp = -0.35 V, up = 240 cm2 /vsec, W = 700 nm, L = 350 nm Compute the resistance Rp for PMOS if the power supply voltage (Vdd) is 3.3 volts and the threshold voltage is 0.35 volts. Use the multiplying adjustment factor as 2.5. Please choose one of the following. You must indicate your answer. No partial credit is given for your work. (a) 16.98M Ohms, (b)1870.24 Ohms, (c) 25.55K Ohms, (d) 72.88 Ohms, (e) None
In the above figure, v1 is a square wave, ranging from 0 to VDD at frequency fCLK. How much power is dissipated in a CMOS integrated circuit containing the equivalent of 500 Million of the above inverters if we assume that 98% of the inverters are static and the other 2% are switching at a clock rate of 1GHz? 225 W 1.13 kW 30 W 450 mW 45 W Electrically-matched devices Kn = Kp = 10 μA/V2 VTN = -VTP = 300 mV λn = λp = 0 V-1
For the following amplifier with PMOS current source load assume NMOS (W/L)1 = 50/0.5, PMOS (W/L)2 = 50/2 and ID1 = ID2 = 0.5 mA when both devices are in saturation. (Given: μnCox = 1.34 × 10-4 A/V2, μpCox = 3.8 × 10-5 A/V2, λp = 0.05, λn = 0.1, VDD = 3 V). Calculate the small signal voltage gain and the maximum output voltage swing while both the devices are saturated.
Emitter follower: The figure below shows a common base amplifier using an NPN BJT which has a common emitter current gain of β = 200, and a base-emitter voltage of VBE = 0.7 V. Ignore the Early effect, i.e. take VA = ∞. The resistor values are RE = 4.7 kΩ, RB1 = 43 kΩ and RB2 = 56 kΩ. The supply voltages are ±5 V. The collector current is IC ≅ 1 mA. a) Draw the small-signal equivalent circuit b) Calculate the transistor's small signal transconductance gm, and the small signal input resistance rπ. c) Calculate the unloaded voltage gain, Avo, input resistance Rin and output resistance Rout of the amplifier. d) What are the loaded voltage gain, Av and overall gain Gv if Rsig = 1kΩ and RL = 1kΩ?
For the circuit below, choose the load impedance Zload so that the power dissipated in it is a maximum. Calculate the power (write answer to the nearest tenth X.X). Use V = 34∠37∘V, R1 = 22 Ω, ZC = -19jΩ, ZL = j4Ω
In the above figure, vI is a square wave, ranging from 0 to VDD at frequency fCLK. Find the inverter’s low and high noise margin values. NML, NMH values: 638 mV, 488 mV 638 mV, 638 mV 488 mV, 488 mV 638 mV, 863 mV 863 mV, 863 mV MOSFET Parameters: Electrically-matched devices Kn = Kp = 10 µA/V2 VTN = -VTP = 300 mV λn = λp = 0 V-1
The switch in the circuit has been in position “a” for a long time. At t = 0 it is moved to position “b”. Find the current and the voltage on the inductor as a function of time, after the switch is moved to position “b”.
For the circuit shown in figure (a) the transistor has β = 200. a) What is the dc voltage at the collector? b) Replace the BJT with the T model of figure (b) and draw the ac equivalent circuit. c) Find the value of re d) Find the voltage gain Av = vo/vi.