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  • Electrical Engineering Archive: Questions from 2024-01-7

    Problem 1: Consider 0.6µm CMOS technology (also known as 0.5µm CMOS) n-well process (p-substrate is lowest potential) with VTN0 = -VTP0 = 0.7 V, µnCOX = 115µA/V2 , µpCox = 50µA/V2 , λ = 0.1 V-1 , γ = 0. Ignore the channel-length modulation effect at the DC analysis onlv, use VDD = 1.8 V, Ix = 100µA, Vout is taken from the drain of Q1 and assume all transistors are in saturation with Lall_transistors = 1µm, Wn = 2µm and Wp = 1µm. Answer the following: a) Calculate de value of yIN that gives a de drain current in M1 of 110µA. b) Calculate the Amplifier input and output resistances. ( Rin, and Rout ) c) Calculate the overall voltage gain,

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    Design an inverter circuit as shown below. You can set the supply voltage (VDD) to 3V. You can get NMOS and PMOS channel lengths (I) 0.2µm. Take the following parameters into consideration when adjusting NMOS and PMOS channel widths (w). 1. Set the threshold value (VTH) = 1.5 V. 2. Delay from 50% to 50% when driving 50fF load = T = 7 × 1ps a) Show that the numerical threshold value is 1.5 V by performing a DC sweep. b) Show the operation of the circuit and the delays with transient analysis. Note: You can take 100MHz as the input signal frequency. Do it using the It spice program and explain it to me step by step, including showing the entry points of the values.

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    The parameters of the circuit given below are VDD = 3.3 V and RD = 5kΩ. The transistor parameters are kn’ = 100µA/V2, W/L = 40, VTN = 0.4 V and λ = 0.025 V-1 . Assume the transistor is biased in the saturation region. (a) Find IDQ and VGSQ such that VDSQ = 1.5 V (b) Determine the small-signal voltage gain

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    The small-signal parameters of an enhancement-mode MOSFET source follower are gm = 5 mA/V and r0 = 100kΩ. (a) Determine the no-load small-signal voltage gain (b) Find the small-signal voltage gain when a load resistance RS = 5kΩ is connected

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    Q1 (15 points): Transistors M1 and M2 are in the saturation region and assume λ ≠ 0, γ = 0. i. ( 10 points) Derive the input-referred 1/f and thermal noise voltage of the circuit depicted in Fig. 1. Neglect the thermal noise of transistors (M1 and M2) and channel length modulation for M1. ii. ( 5 points) Find an expression for the corner frequency. Hints: Flicker Noise for MOSFET: Vn ̅2 = K/CoxWLf Thermal Noise for a resistor: Vn 2 = 4kTR

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    Design the following complete addition circuit using the LT Spice program. You can get NMOS and PMOS channel lengths (I) 0.2μm. a) Derive the truth table of the circuit. b) Show that the circuit performs full additive function by performing DC operating point analysis and Transient analysis.

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    24.13 Calculate the total channel area for a symmetric two-input CMOS NAND gate using (a) WN/LN = 4μm/2μm for the NMOS transistors (b) WP/LP = 4μm/2μm for the PMOS transistors

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