The circuit below is a common-source stage followed by a common-gate stage (Why?). (a) Determine the voltage gain vout/vin = (vout/vX)(vX/vin) assuming λ = 0. (b) Simplify the result obtained in (a) if RD1 → ∞. Explain why this result is to be expected. Consider the circuit of Fig. 7.72, where a common-source stage (M1 and RD1) is followed by a common-gate stage (M2 and RD2). (a) Writing vout /vin = (vX/vin)(vout/vX) and assuming λ = 0, compute the overall voltage gain. (b) Simplify the result obtained in (a) if RD1 → ∞. Explain why this result is to be expected. Figure 7.72 17.45. Consider the circuit of Fig. 17.113, where a common-source stage (M1 and RD1) is followed by a common-gate stage (M2 and RD2).
Problem 2: In the following circuit, (W/L)1 = 20 and (W/L) 2 = 30. (a) What is the vIN value for vOUT = 1.5 V? Please consider the channel modulation effect and the bulk effect. (b) Calculate the small signal voltage gain (vout/vin) , input resistance (rin), and output resistance (rout) at the above biasing point.
Figure 4: Circuit Diagram for Q.3 For the circuit diagram in Figure 4, the NMOS and PMOS were fabricated in a process where μnCox = 120 μA/V2, μpCox = 60 μA/V2, Vtn = −Vtp = 1 V. (a) Find the value of the voltage marked at Vy (b) Determine the width ratio of NMOS and PMOS of the inverter when Vinv = (Vy -0.5)V. (c) Given, VOL = 0 V and VOH = 5 V for the inverter shown in the circuit. Identify the High and Low Noise Margins for an inverter added after Vout which has VIH = 3.9 V and VIL = 1.2 V.
Observe the I-V characteristics of an nMOS transistor as shown in Figure 1 and answer the following questions: Figure 1: I-V characteristics of an nMOS transistor Consider threshold voltage, electron mobility, gate oxide thickness and permittivity to be 0.2 V, 450 cm2/V.s, 1 nm and 3.9 × 8.85 × 10 −14 F/cm respectively. The drain to source current increases until Vds = 0.6 V. (a) Evaluate Vgs. (b) Calculate the aspect ratio (W/L) of the mosfet. 7 (c) Find the current when Vds = 0.8 V. Comment on the current through the device if the drain-source voltage is further increased.
Q.1. For amplifier shown below VDD = 2.5 V. All transistors are in saturation. Neglect body effect. Channel length modulation is to be neglected for DC analysis. Find: - (i) The DC voltage at the gates of the pMOSFETs. (ii) Small signal output resistance at node Vout. (2) (iii) Small signal differential gain (2) Total 6 Marks