A 0.18-μm fabrication process is specified to have tox = 4 nm, μn = 450 cm2/V⋅s, and Vthn = 0.5 V. The dielectric constant of the silicon dioxide is 3.9. Find the value of the process transconductance parameter. For a MOSFET with minimum length fabricated in this process, find the required value of W so that the device exhibits a channel resistance rDS of 1 kΩ at vGS = 1 V. Ans. 388 μA/V2; 0.93 μm.
Problem 1: Static CMOS Circuit A transmission gate is a simple structure composed of two transistors which operates like a switch. Answer the follow questions to understand their functionality and use. What is the benefit of using a transmission gate compared to a single transistor? Explain in words how a transmission gate functions when a single input and its complement are presented to the NMOS and PMOS gates respectively as shown below How can a transmission gate be used to tri-state the output of a gate? For example, as wit a tri-state buffer?
P8.6. Consider the NMOS gate shown in Figure 8.35. Determine the value of VOUT if VA = 5 V and VB = VC = 0 V. (This is the worst case of VOL.) Determine the value of VOUT if VA = VB = VC = 5 V. FIGURE 8.35 NMOS gate (P8.6).
For the following circuit, use Rs = 100 Ω, C1 = 10 μF, R1 = 1 KΩ, R2 = 220 KΩ, R3 = 1.5 kΩ, RL = 500 Ω, VCC = + 15 V, −VEE = −15 V, and β = 100. a. Confirm that the circuit is in the active mode b. Draw the small signal model of the circuit c. Find the amplifier's ac gain (vout/vin with source and load removed) d. Find the small signal input resistance (with the load attached) e. Find the small signal output resistance (with the source attached) f. Sketch the simplified model for the amplifier g. Find the voltage gain of the circuit (with the source and load attached) h. Find the current gain of the circuit (with the source and load attached)
10.13 A CMOS inverter fabricated in the process specified in Problem 10.12 utilizes a p-channel device four times as wide as the n-channel device. If the VDD supply is subject to very-high-frequency noise and there is an equivalent load capacitance of 1 pF, what is the 3-dB cutoff frequency embodied in each gate for this supply noise?
Small signal gain and impedance a) Show the small-signal model to find Vout/Vin. M1, M2, M3 has an infinite output impedance (rds = infinite). Vb is a bias voltage. Assume all saturated. (5pt) b) Find the small signal gain defined by Vout/vin. (10pt) c) Find the small signal output impedance (5pt). d) Find the small signal input impedance (5pt).
In this problem, we will analyze the noise margins for chains of gates. Figure 1(a) a) First, let's consider Figure 1(a). Add to the chain the DC voltage sources that you would use for modeling noise coupling to the input and output of gate M2. You should arrange these voltage sources so that they would both impact the noise margin in the same way (i. e., if the voltage source at the input decreases the noise margin, the voltage source at the output should also decrease the noise margin). Figure 1(b) b) Figure 1(b) shows the VTC of gates M1, M2, M3, respectively. For each stand-alone gate: i. Compute the numerical values in Volts of the noise margins. ii. Draw the butterfly diagram of the gate. iii. Determine whether the gate is digital or not. c) Now consider only the cascade of M2 and M3. For this part: i. Determine the VTC of the cascade. ii. Compute the numerical values in Volts of the noise margins. iii. Determine whether the cascade of the two gates is digital or not.
A D-latch is given in the Figure 1. There are 2 identical CMOS inverters with the VTC given in Figure 2. In this system, logic '1' (high) is 1.5 V and logic '0' (low) is 0 V. For the MP transistor, constant reverse leakage current is 1 μA and subthreshold current is 250 nA. Threshold voltage of MP is VT,nmos = 0.4 V. Cx is 20 nF. Figure 1: A Dynamic Logic Circuit Figure 2: VTC of the inverters. a. What is the maximum voltage value that can be observed at Vx? b. Worst-case holding time (thold) is defined as the shortest time required for the soft-node voltage drop from its initial high value to the logic threshold value due to the leakage. Consider the VTC and calculate thold.