Consider the circuit drawn at right. The transistor parameters are k = 3 mA/V2, VT = 1 V. Hint: Assume transistor in Saturation, and then check answers at the end. Remember: Single-subscript voltage such as "VG" means voltage at point VG relative to ground. Double-subscript voltage such as "VGS" means VG−VS. a) Draw the equivalent large-signal circuit model. b) How much current flows into the gate? Justify your answer. c) Find VG. [Hint: think about the implication of your answer to (a)] d) Find Vs. [Hint: it's not zero; 2 equations, 2 unknowns Vs and Io] e) Find I0. f) Find VD. [Hint: once you know ID, you can calculate voltage drop through RD] g) Confirm transistor in saturation.
The circuit given below has the voltage transfer characteristic curve shown on the right. When Vin = 5 V, the circuit consumes 12 mW of power. Find the values of VDD, R, Kn and VTN.
In this Dynamic N-Tree Gate, the supply voltage equals 0.9 V. If A, B = 0 during Precharge phase and both transition to '1' during Evaluate phase of the Clock, determine the voltages of X, Y and Z. What is the maximum leakage that can be tolerated assuming a cycle time of 1 ns if A, B = 0 during the evaluate phase and the logic threshold of the inverter driven by this gate is 0.7 V?
A MOS differential amplifier is driven with an input CM level of 1.6 V. If I S S (biasing current source) is 0.5 mA, Vt = 0.5 V, and VDD = 1.8 V, what is the maximum allowable load resistance (RD)? Hint: What is required for the transistors to be in saturation? 3.5 KOhm 2.8 KOhm 1.0 KOhm 7.50 KOhm
Design the circuit below to obtain a dc voltage of 0 V at each of the drains of Q1 and Q2 when vG1 = vG2 = 0 V. Operate all transistors at VOV = 0.15 V and assume that for the process technology in which the circuit is fabricated, Vtn = 0.35 V and μnCox = 400 μA/V2. Ignore channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, Q3, and Q4. What is the input common-mode voltage range for your design? Hint: The lower limit on VCM is determined by the need to keep Q3 operating in saturation and the upper limit on VCM is determined by the need to keep Q1 and Q2 in saturation.
(25 pts) SP-2. Consider the transmission gate circuit shown in Figure 1 with Vt = Vtn = |Vtp|. Figure 1. Transmission gate circuit (a) In the steady state with X = 1, derive an expression for the energy stored in the capacitor. (b) If the nMOS transistor is faulty (always OFF), derive an expression for the steady state energy stored in the capacitor with X = 1. (c) If the pMOS transistor is faulty (always OFF), derive the expression for the steady state energy stored in the capacitor with X = 1. (d) Assume that VOUT = 0 V at t = 0. If X is now switched from 0 to 1, derive an expression for the energy lost in the transmission gate with a faulty pMOS transistor (always OFF).
b) Circuit below is used for testing a power MOSFET. Testing is done under following conditions: Vdc = 90 V, R = 5 Ω, Von = 0.09 V (Vds voltage drop in on-state), switching frequency fSW = 8 kHz and duty cycle d = 0.65. Calculate the current through the MOSFET when it is on, and the conduction losses. [9 marks] Ids = Number A Pcond = Number W
(b) For a MOSFET current source shown in Figure 3, the bias voltages are V+ = 1.5 V and V− = −1.5 V. Transistors are available with the parameters: kn' = 200 μA/V2, VTN = 0.5 V, and λ = 0. Figure 3 (i) Design the circuit such that IREF = 100 μA, IO = 250 μA, and VDS2(sat) = 1 V. [10 Marks] (ii) Calculate the change in output current, dIo and hence the output current Io when VDS2 = 3 V. Let λ = 0.01 V−1.
(a) For an NMOS Wilson current source as shown in Figure 4, transistor parameters are: VTN = 0.8 V, λ = 0.02 V−1, Kn1 = 2Kn2 = 3Kn3 = 0.25 mA/V2. Given IREF = 0.5 mA. If the voltage VD changes by 2 V, what is the percentage change in the output current? [13 Marks] Figure 4
(b) For a MOSFET current source shown in Figure 5 the circuit parameters are: V+ = 3 V and V − = −3 V. Transistor parameters for NMOS are: VTN = 0.7 V, kn′ = 200 μA/V2 and λn = 0.01 V−1; and the transistor parameters for PMOS are: VTP = −0.6 V, kp′ = 80 μA/V2 and λp = 0.03 V−1. The transistor aspect ratios are: (W/L)1 = 10, (W/L)2 = 35, (W/L)3 = 5 and (W/L)4 = 15. Find IO, IREF and the VGS voltages for all transistors if the minimum voltage at the drain of transistor M2, i.e. VD2 is −2.3 V. [12 Marks] Figure 5