Given a symmetrical inverter on the left. Size the transistors in the circuit to the right for worst-case pull-up and pull-down that match the current drive of the inverter
The switch in the following circuit has been closed for a long time. At t = 0, it is opened. a) Write the expression for the current iL(t). b) Write the expression for the current io(t). c) Write the expression for the voltage vx(t). d) Write the expression for the power dissipated in the 26 Ω resistor. e) Sketch the power in dissipated in the 26 Ω resistor. f) Calculate the total energy dissipated in the 26 Ω resistor.
i) Write the Boolean expression for OUT of the following circuit. ii) VDD = 2.0 V and Vtn = 0.5 V. During precharge (Clk=0), All inputs are logic 0. During evaluation (Clk=1), A and B are activated (0→1). What is the final voltage when the evaluation mode settles?
For the circuit shown below, calculate the cutoff frequency (3dB frequency) at node X. Assume the voltage gain from the gate of M1 to the source of M1 is 0.9 V/V. Assume ideal Vdd and IBias. (Consider capacitance Cgs and Cgd only.) (20 points) M1 Cgs = 200fF Cgd = 20fF
Problem 1: An n-channel enhancement-mode MOSFET with parameters VTR = 2 V and K = 1 mA/V2 is connected to the circuit below with VDD = 10 V and RD = 1 kΩ. (a) Plot the v−i characteristics of the MOSFET for VTR < VGS < 8 and 0 ≤ VDS ≤ 10 V. (b) Draw the load line imposed by VDD and RD over this set of v−I characteristics. (c) Graphically determine the transfer characteristic of the inverter over the range 0 < vIN < 8 V.
The circuit shown in Figure 1 is a modified Widlar current source. Given that the size ratios of M3:M4 = 1:1 and M5:M6 = 1:1. (a) Find the expression of IB in terms of circuit parameters: VTHN, μnCox, R1, (W/L)1 and (W/L)2. (3 marks) (b) Find the expression of the minimum VDD when only looking at current branch 1. ( 3 marks) (c) Find the expression of the minimum VDD when only looking at current branch 2. (3 marks) (d) Based on results in (b) and (c), find the minimum VDD. (1 mark) Figure 1
Q. A CMOS pair is used, as shown in the circuit above, to switch an LED on and off using an input voltage that is either 5V or 0V, at different times A, B, C, etc. Summarize the switching action by filling in the table below. Explain your reasoning briefly. Assuming 2 V across the LED when it is on, determine the value of the output resistor if the device current in the on state is 1 mA.
Consider the CMOS amplifier in the common-source configuration from the figure, for the case: VDD = 5 V, Vtn = |Vtp| = 1 V, μnCox = μpCox = 20 μA/V2, W = 100 μm, L = 10 μm, for both types of NMOS, PMOS transistors, and IREF = 100 μA. (i) Assuming all transistors operate in saturation, working with first-order equations, establish the range of output voltage corresponding to the amplifying region, that is, the values VOA′ and VOB′. (ii) Considering |VA| = 100 V for both types of transistors, obtain the small-signal gain vo/vi in the mid-frequency range.
The differential amplifier provided utilizes a resistor Rss = 1.5 kΩ to establish a 1 mA dc bias current. Note that this amplifier uses a single 5 V supply and thus the dc common-mode voltage Vcm cannot be zero. Transistors Q1 and Q2 have identical parameters given by: Kn = 3 mA/V2 Vthn = 0.7 Vλ = 0 Find the minimum required value of Vcm. Find the value of RD that results in a differential gain Aid of 3 V/V. Determine the dc voltage at the drains of Q1 and Q2. Determine the common-mode gain Acm. Vcm(min) = VRD = kΩ VD1 = v VD2 = v Acm = V/V
The transistors have the following characteristics: nMOS: Vtn = 0.5 V, Kn′ = 400 μA/V2; pMOS: Vtp = −0.5 V, Kp′ = 100 μA/V2; Also assume Mn1, Mn2 and Mn3 have (W/L) = 2; Mn4 and Mn5 have (W/L) = 4; Mp1 and Mp2 have (W/L) = 8; and Mp3 and Mp4 have (W/L) = 16. (a) Assume VDD = 5 V. Find the voltages VGP3, VGP4, VGn5 and the current ID shown in the figure (20 points). (b) What would be the DC voltage of the signal (VGn4) for proper operation? (5 points) (c) Find the small signal gain (vo/vin) of the amplifier. Assume all transistors have |λ| = 0.05 V−1 ( 10 points). (d) Find the allowable voltage swing (vo-max and vo-min) at the output node to keep all transistors in saturation. (15 points)
In the circuit configurations below: a. Identify Drain and Source terminals assuming the device is an NMOS. b. Identify operating region of each transistor (cutoff, saturation, or velocity saturation). c. Determine the drain current Assume VDS at = 1 V, VTN = 0.5 V, and K′n(W/L) = 1 mA/V2. Ignore the body effect. (a) (b) (c) (d) (e) (f) (g)