For the Common-Drain (source-follower) configuration below: a) Draw the small-signal T-model of the circuit (Include the channel length modulation effect). b) Consider that the MOSFET operates with ID = 1. 111 mA, gm = 1 mA/V and that the channel length modulation effect must be included with λ = 10 mV−1. Find the output resistance Ro and the overall gain Gv?
Analyze the following common gate amplifier that uses a NMOS transistor: a) Draw the small-signal T-model of the circuit (Ignore channel length modulation effect). b) Find the expressions for Rin, Av = vO/vi and Gv = vO/vsig
A NMOS transistor is fabricated with one of the latest process technologies for which L = 3 nm, W = 75 nm, tox = 0. 4 nm and μn = 1450 cm2/V.s. a) Find Cox, kn′ and Kn. Don't forget to add the units and be careful with them! (Hint: Use εox = 34. 515×10−12F/m) b) Assuming this transistor is modified to have Kn = 2 mA/V2 and Vtn = 1 V, analyze the following circuit to determine all the voltages and currents. Start assuming triode operation, but don't forget to check if the assumption is correct. (Ignore channel length modulation effect, λ = 0 ) c) For the same NMOS transistor, if VGS becomes now 5 V and VDS is kept very small, find the equivalent resistance of the channel.
Consider the amplifier below, VDD = 3.3V, ISS1 = ISS2 = 40μA, the size of all transistors are 20, and the minimum voltage to keep each of Iss1 and ISS2 function as a current source is 0.4V. Ignore bulk effect. (a) (10 points) What is the input common mode range to keep all transistors saturated? (b) (10 points) What is the low frequency differential voltage gain? (c) (10 points) What is the CMRR?
In the base biased JFET circuit is shown below, VDD = 12 V, IDSS = 9 mA, VP = 6 V, and VGG = 0 V. i) Find the value of RD required to operate the transistor at VDS = 7 V. ii) The plot shown on the right is the VDS−ID characteristic for the JFET. On that plot (or on a neat redrawing of that), mark all relevant numbers and also draw the load line.
Implement the following function using nMOS and pMOS transistors. Consider the circuit in Figure 1 with the following parameters: tsetup = 0.25, thold = 0, tpcq = 0.75, tccq = 0.25, tpd1 = 2, tpd2 = 2, tpd3 = 1.5, tpd4 = 2.5. (a) What is the minimum value for TCLK in the given circuit? What is the latency and throughput of the circuit. (b) Guided by the concept of pipelining, draw an enhanced circuit by adding an additional 3 filp-flops (between the 4 components) to obtain an improved throughput. Compute in detail what the new value of TCLK may be, and what the corresponding latency and throughput are. Figure 1: A circuit with 4 components.
(a) Compute the Noise Margins (NMH and NML) for the following parameter values: VOL = 0. 2, VIL = 0. 5, VIH = 2. 5, VOH = 3, VDD = 4. (b) Use Figure 2 below to plot the output voltage as a function of the input voltage of a potential NOT gate that has the parameters above. Add all details to your plot. Namely, label each vertical and horizontal line with one of the values: 0, VOL, VIL, VIH, VOH, or VDD and plot your curve. Note that the vertical and horizontal lines in the figure are not to scale. Make sure that your curve satisfies the conditions stated in class with respect to the significance of the variables VOL, VIL, VIH, VOH, and VDD. Figure 2: Output voltage as a function of input voltage for a NOT gate.
Sedra Smith textbook - problem 9. 12 [15pts] An NMOS differential amplifier (as shown), is operated at a bias current I of 0. 2 mA, has K = 6.4 mA/V2, and RD1 = RD2 = RD = 10 kΩ. [Assume that VA is large and can be ignored]. Find gm, and Ad. [Hint: You may want to manipulate the transconductance equation and then combine it with the saturation current equation.]