(b) In the inverter chain given by Figure 4, there are several "ghost" inverters S2' and S3' are "copying" the behaviors of inverters S2 and S3, respectively. Assume that CL1 = 108Cg,1, CL2 = 18Cg,1. (1) Determine the size of the inverters in the circuit such that the delay between node OUT and IN are minimized. (2) Determine the size of the inverters in the circuit such that the delay between node OUT and IN are minimized. Assume that VDD = 3 V, Cg,1 = 1 fF, INPUT is connected to a clock signal generator with frequency f = 1 GHz, switching between 0 V and 3 V. Assume that each stage of the Inverter chain could successfully react to the INPUT, which means tpHL+tpLH < 1 f. Determine the total power dissipated by the minimized inverter chain. Figure 4: Inverter Chain for Problem 2-b
17.16 A matched CMOS inverter fabricated in a process for which Cox = 25 fF/μm2, μnCox = 500 μA/V2, μpCox = 125 μA/V2, Vtn = |Vtp| = 0.35 V, and VDD = 1.0 V, uses Wn = 260 nm and Ln = Lp = 65 nm. The overlap capacitance and the effective drain-body capacitance per micrometer of gate width are 0.3 fF and 0.5 fF, respectively. The wiring capacitance is Cw = 2 fF. If the inverter is driving another identical inverter, find tPHL, tPLH, and tp. For how much additional capacitance load does the propagation delay increase by 50%? tPHL = tPLH = tp = 7.7 ps; 3.16 fF
For the band gap reference shown above M1, M2, and M3 are identical. a. We size one BJT n times the other BJT. Which one should be larger and why? If the larger BJT has an area of nA then its saturation current is nIs of the smaller BJT (with an area of A and saturation current of Is) b. The OPAMP should be in negative feedback for the circuit to function properly. Explain that the OPAMP is in negative feedback in the shown configuration. c. Find the output voltage Vout.
Assume that tpd is the average of tPHL and tPLH. Find the delay from each input to the output in Figure 2-41 by (a) Finding tPHL and tPLH for each path, assuming tPHL = 0.20 ns and tPLH = 0.36 ns for each gate. From these values, find tpd for each path. (b) Using tpd = 0.28 ns for each gate. (c) Compare your answers from parts (a) and (b) and discuss any differences. FIGURE 2-41