Describe the difference between NMOS and PMOS. Find a logic equation for 1 bit adder circuit; Out = A + B. Find logic equation of a given truth table, and draw logic circuit. Construct a CMOS circuit to implement the above logic equation and describe operation of your circuit. When input A is at Vdd, input B is at supply voltage (Vdd), and input C is at GND, which transistors are ON, which ones are OFF, and what is output voltage of your circuit). According to your answer in question 2, what input combination has the fastest and slowest delay.
P11.52. Consider the amplifier shown in Figure P11.52. a. Draw the small-signal equivalent circuit, assuming that the capacitors are short circuits for the signal. b. Assume that rd = ∞, and derive expressions for the voltage gain, input resistance, and output resistance. c. Find IDQ if R = 100 kΩ, Rf = 100 kΩ, RD = 3 kΩ, RL = 10 kΩ, VDD = 20 V, Vto = 5 V, and K = 1 mA/V2. Determine the value of gm at the Q point. d. Evaluate the expressions found in part (b) by using the values given in part (c). e. Find vo(t) if v(t) = 0.2 sin(2000πt). f. Is this amplifier inverting or noninverting? Figure P11.52
For the circuit below, VCC = 20 V, VBE1 = VBE2 = 0.8 V, β = 300, VT = 25 mV, VA = ∞, R1 = 230 kΩ, R2 = 120 kΩ, RC1 = 12 kΩ, RC2 = 6 kΩ, RE1 = 500 Ω, RE2 = 3 kΩ, and RE3 = 4.5 kΩ are given. C∞s are very large coupling/bypass capacitors. a. Find the operating collector currents of T1 and T2. Neglect the base currents and assume α = 1. b. Find the value of RL1 such that the second stage output has symmetric clipping property. Assume VCEsat = 1.5 V. c. What is the voltage gain of the amplifier in dB ? d. Now, assume that the amplifier should drive a load of RL2 = 270 Ω. For this purpose, the circuit on the right is coupled to the node X in the multi-stage amplifier. Explain why this circuit has been preferred. a. Find the value of IDC given that kn,T3 = 30 mA/V2 and λ = 0, such that the voltage gain of the newly-added stage is AV, T3 = 0.9. Assume that T3 operates in the saturation region.
Topic: Instrumentation Amplifier Question: a) Write down the general form of differential gain Ad. b) Write down the individual gain factors of A1 and A2. c) Take R4 = 100 kΩ, R3 = 10 kΩ, R1 = 10 kΩ, R2 = 90 kΩ. Calculate Ad. d) Write down the general form of differential gain Ad′ if there is a mismatch in resistors R2 and calculate the new differential gain with R2′ = 10 kΩ.
P1. The C−V curves measured for two MOS capacitors ( a and b ) with the same gate area are compared below. a) Explain the differences and similarities between these two capacitors. b) Draw the C-V curve of capacitor b when it is exposed to light.
P2. For a capacitor of area 100 μm×100 μm operated at T = 300 K, with ΦM = 5.2 eV, xox = 3 nm, and ND = 1017 cm−3 a) Calculate the flat band capacitance and threshold voltage b) Draw the low frequency and high frequency CV curves
P3. In a MOSFET with Z = L = 5 μm, the polysilicon gate with Fermi level of 0.1 eV above the conduction band edge is used. tax = 300 Å and μn = 550 cm2/N-s. There is a fixed oxide charge of Qf = 2×10−8 Coulombs/cm2 positioned midway between the gate and the substrate. Na = 1016 at/cm−3 a) What is VFB? b) What is VT? c) Using the square law and VG = 5 V, what is IDsat? d) Plot the C−V curve and numerically label the important points. Qualitatively, how does the curve shift if the substrate and poly dopings are switched from n to p and vice versa? e) Sketch a band diagram along the "channel" (the dotted line "a") for the device if VG = 0 V. Numerically label the band offsets.
Consider the circuit in Figure 1. Given that the VTN = 0.4 V, VTP = −0.4 V, kN = kP = 100 (mA/V2), VDD = 1.8 V. (1) When the Vi = 0.6 V, find the output voltage. Indicate that which one works like a resistor and find the value of the equivalent resistor, draw the ID− VDS diagram and please label clearly. (2) And now the Vi = 1.2 V, re-do the problem (1). (3) If the application is an analog inverter, what is the range of the input signal? Consider the circuit in Figure 2. Assume the Rsig ≅ 0. Given that VDD = 10 V, vsig (t) = 0.5×sin(2000πt) V, RD = 100 Ω, R1 = 1 MegΩ, R2 = 1 MegΩ. (VTN = 2 V, kN = 10 (mA/V2)) (1) Find the operating point Q. (Draw the load line and ID−VDS diagram.) (2) Find the gm. (3) Find the vD. (4) Sketch the vGS − t, vD−t.
Calculate the small signal voltage gain of the CS amplifier with RS if IBIAS = 1 mA, RD = 1 kΩ, RL = 2 kΩ, RS = 100 Ω and VDD = 2.5 V NMOS has VT = 0.5 V, μnCox = 100 μA/V2, W/L = 10 μm/0.18 μm and λ = 0 Determine VBIAS such that the NMOS transistor operates in saturation if the minimum required voltage drop of the current source is 0.5 V Solution: Av = −1.7 V/V and 1.7 V ≤ VBIAS ≤ 2 V