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  • Electrical Engineering Archive: Questions from 2024-07-5

    A Schottky barrier source and drain MOSFET has been under study as an approach to reduce the source and drain resistance and eliminate latch up. A schematic of this device is shown below. This problem is about drawing energy band diagrams in order to understand its basic operation. Consider a device with a threshold voltage VT = 0.5 V, body doping level NA = 1017 cm−3, and source and drain Schottky barrier height qφBp = 0.5 eV. The gate is made up of n+ polySi. (a) Sketch an energy band diagram right along the surface of the device (cross section A−A′ above) for VGS = 1 V and VDS = 0. Give as many values of key energy features as you can. (b) Sketch an energy band diagram right along the surface of the device (cross section A−A′ above) for VGS = VDS = 1 V. Give as many values of key energy features as you can. (c) How does this device operate? Can you see any drawbacks?

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    Consider the output I−V characteristics of a long-channel n-MOSFET for VSB = 0 below. The device has a gate length Lg = 1 μm and a gate oxide thickness xox = 10 nm. The output characteristics have been normalized for a unity width device. (a) Assuming that this device is an ideal long-channel MOSFET, estimate its threshold voltage. (b) Assuming that this device is an ideal long-channel MOSFET, estimate the mobility of the electron inversion layer. (c) Assuming that this device is an ideal long-channel MOSFET, estimate the transconductance gm at a bias of VGS = 3 V and VDS = 3 V for Wg = 10 μm. (d) At a bias of VGS = 3 V and VDS = 3 V, estimate the gate-source capacitance Cgs of a Wg = 10 μm device. (e) Now you are given the additional information that the subthreshold swing of this transistor technology at room temperature is S = 78 mV/dec. At a bias of VGS = 3 V and VDS = 3 V, estimate the back-gate transconductance gmb of a Wg = 10 μm device. (f) At a bias of VGS = 3 V and VDS = 3 V, how much less current do you expect to have as a result of the body effect? (Consider the additional subthreshold current information, if needed.)

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    (a) An ideal n-channel MOSFET has parameters tax = 18 nm = 180Å, μn = 450 cm2 /V−s, and VT = 0.4 V. The measured current in the saturation region is ID( sat ) = 0.8 mA when biased at VGS = 2.0 V. Determine the (i) process conduction parameter and (ii) width-to-length ratio. (b) An ideal p-channel MOSFET has the same oxide thickness as given in part (a), a mobility of μp = 210 cm2 /V-s, and a threshold voltage of VT = −0.4 V. The measured current in the saturation region is also ID( sat ) = 0.8 mA when biased at VSG = 2.0 V. Determine the (i) process conduction parameter and (ii) width-to-length ratio.

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    For the circuit given, transistor parameters are β = 100, VBE = 0.7 V, Vth,p = −1 V, μpCox(W/L) = 50 μA/V2. a) Design a bias stable circuit that BJT operates at the active region and MOS transistor operates at saturation region. b) Find the voltage gain, vo/vs

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