5.16. The circuit of Fig. 5.115 is designed for a collector current of 0.25 mA. Assume IS = 6×10−16 A, β = 100, and VA = ∞. (a) Determine the required value of R1. (b) What is the error in IC if RE deviates from its nominal value by 5%? Figure 5.115
Design a single-stage CS amplifier (Fig. 1) with CSL for the following specifications. You may refer to the design steps taught in the Lecture 3. Supply voltage (VDD): 1.8 V (Single supply) Open-loop DC Gain: > 40 Output voltage swing: > 1.0 Vp−p DC output voltage: ∼0.9 V Total current: < 0.4 mA Maximum channel width: 500 μm Fig. 1
The following circuit uses an ideal Op-Amp. Assuming that vin = 6.6 mV, R1 = 9 kΩ, R2 = R4 = 26 kΩ, and R3 = 8 kΩ Find the current i4 in micro Amps
Problem 2 (2 pts) - nFETs Given the circuit on the right, determine the mode of operation (saturation or triode) and find the DC value of IOUT. M1 and M2 have identical fabrication parameters. a) Solve using above threshold equations. Ignore the Early and body effects b) Solve using subthreshold equations. Ignore the Early effect.
16.18 For a particular inverter design using a power supply VDD, VOL = 0.1VDD, VOH = 0.8VDD, VIL = 0.25VDD, and VIH = 0.6VDD. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 0.25 V, what value of VDD is required? Show Answer
Calculate the noise margin high (NMH) and noise margin low (NML) for each pair of logic gates specified below. Refer to the data sheets provided on Blackboard. (a) driver: 74F04 (d) driver: 74LS04 load: 74F04 load: 74F04 (b) driver: 74F04 (e) driver: 74HC04 load: 74LS04 load: 74F04 (c) driver: 74F04 load: 74HC04
a. The low noise margin (NML) is less than the high noise margin (NMH) b. When vI = VDD/2, the p-channel MOSFET is biased in triode. c. The n-channel MOSFET is biased in saturation when vI = VIL. d. The electron and hole mobilities are assumed to be equal. Answer: a Answer: b Answer: c Answer: d
A 7.0−μF and a 3.0−μF capacitor are connected in series across a 24−V battery. What voltage is required to charge a parallel combination of the two capacitors to the same total energy (in Volts)?
How many 1.35 μF capacitors must be connected in parallel to store a charge of 1.00 C with a potential of 144 V across the capacitors?
A 1.76−μF and a 4.92−μF capacitor are connected to a 62.0−V battery. What is the total charge supplied to the capacitors when they are wired (a) in parallel and (b) in series with each other?
A silicon diode has a forward voltage drop of 1.2 V for a forward dc current of 100 mA. It has a reverse current of 1 μA for a reverse voltage of 10 V. The barrier potential voltage is 0.7 V and kT/q = 25.7 mV. (a) (i) Determine the bulk resistance of the diode. (ii) Determine the reverse resistance of the diode. (b) (i) Determine the junction resistance at dc current of 2.5 mA. (ii) Determine the ac resistance at forward dc current of 2.5 mA. (c) (i) Determine the junction resistance at dc current of 25 mA. (ii) Determine the ac resistance at forward dc current of 25 mA. (d) Consider the diode at 290∘K. (i) Derive an expression for the dynamic slope resistance rd = dV/dI from the diode equation. (ii) Determine the dynamic slope when the forward biased current is 10 μA. (iii) Determine the dynamic slope when the forward biased current is 5 mA.
Consider the circuit shown in the diagram below. The potential difference across the points a and b is ΔV = 120.0 V and the capacitors have the following values: C1 = 12.0 μF, C2 = 5.00 μF, C3 = 2.00 μF, and C4 = 10.0 μF. Initially the capacitors are all uncharged. (a) What is the total charge that has to flow through meter A for the capacitors to go from the initial uncharged state to the final state when they are fully charged? mC (b) What is the charge on each fully charged capacitor? Q1 = mC Q2 = mC Q3 = mC Q4 = mC
ajiv Gandhi University of Knowledge Technologics (Department of Electronics and Communication Engineering) MONTHLY TEST - 2 Year/Sem: E2-SEMII Subject: AEC Subject Code:23 EC2101 Date: 17-10-2023 Time: 45 Minutes Max. Marks: 15 Marks Section-A ― Answer the following question. (1 X7 = 7 Marks)a) For the common source amplifier as shown in fig below, Given μaCnt(W/L) = 0.25 mA/V2, Vm = 1.5 V, VA = 50 v (use VA for riscalculation (x≠0) then. Find MILLER'S THEOREM i) small signal voltage gain ii) input resistance and output resistance iii) maximum allowable imput signal (OR)For the Differential amplifier as shown in fig below, Given μ2 Cin = 100 μA/V2, Vti = 1 V, +VDD = +5 V, −VSS = −5 V; Neglect Channel length modulation. Assume M1 and M2 are matched(identical) transistors. find V1, V2 and V3 for the following cases a) (W/L)1 = (W/L)2 = 20 b) (W/L)1 = 1.5(W/L)2 = 20; Section-B Answer the following question. (1 8 = 8 Marka)a)for the MOSFETS shown in circuit μ3 Cm = 50 μA/V2, Vm = 1 V, L = 1. μm, w = 10 μm then find the V 3 and 13 in the circuit. b) For the Differential amplifier given below, Given μnCn = 1 mA/V2, Vn