A DRAM chip utilizes a 1T-1C (one transistor and one capacitor) configuration. The capacitance of each DRAM cell is engineered to preserve the stored data for a minimum of 60 nanoseconds (ns) prior to requiring refreshment. Post-refresh, the voltage across the capacitor is assumed to be 1 V, with a threshold voltage of 0.5 V to ensure the data within the capacitor is not lost, and the capacitance value is 100 pF. a) Calculate the minimum amount of charge that the capacitor needs to retain. b) With a leakage current causing a 10% charge loss from the capacitor in 60 ns, determine the amount of charge lost within 60 ns and whether this meets the design specifications for the refresh period