Problem 2 (18 points) For the circuit below use the following parameters: NMOS: μnCox = 0.4 mA/V2, VTn = 0.6 V, λn = 0 PMOS: μpCox = 0.12 mA/V2, VTp = −0.6 V, λp = 0 The circuit shown must be designed for a voltage drop of 400 mV across Rs. Assume W/L = 12/2 (a) Calculate the minimum allowable value of VDD if M1 must remain in saturation. (b) What are the required values of R1 and R2 if the input impedance must be at least 200 kΩ? (c) Calculate the transconductance and sketch the complete small signal circuit (a) VDDmin = 3.31V (b) R1 = 1045 k, R2 = 247k (c) gm = 2.19m
For the inverter circuit in the below figure, let vI go from VDD (high) to 0 V (low) at t = 0. At t = 0+, vO = 0 V. (a) What is tPHL? Express it with τ. Assume VOH = VDD and VOL = 0. (Hint) vo(t) = VOH − (VOH − VOL)e −t/τ (b) If R = 4.7 kΩ, what is the value of the capacitance C that ensures that tPHL = 100 ps?
Question 2: The CS amplifier stage shown below has a voltage gain of 15 at a bias current of 0.5 mA. Determine the required value of (W/L)2. [7.5-pts] λ1 = 0.15 V−1, λ2 = 0.05 V−1⋅μnCox = 200 μA/V2, μpCox = 100 μA/V2, |Vt| = 0.4 V for both PMOS and NMOS. Vb is a DC bias voltage. Assume both transistors below are in saturation.