Question

Notify Me Bookmark

(ii) A Master-slave D flip-flop is constructed using two positive D latches as shown in the figure below. The D-to-Q delay (i. e. when the latch is enabled the time taken for output of latch to change after input changes) is 4 ns. The minimum propagation delay and the maximum propagation delay of inverter are given as 1 ns and 2 ns respectively. Determine tsetup , thold , tClk-Qmin and tClk-Qmax for the D flip-flop. Give proper justification* for your answers. [10] (∗Full marks will be given only if there is proper explanation for your Answers)

(ii) A Master-slave D flip-flop is constructed using two positive D latches as shown in the figure below. The D-to-Q delay (i. e. when the latch is enabled the time taken for output of latch to change after input changes) is 4 ns. The minimum propagation delay and the maximum propagation delay of inverter are given as 1 ns and 2 ns respectively. Determine tsetup , thold , tClk-Qmin and tClk-Qmax for the D flip-flop. Give proper justification* for your answers. [10] (∗Full marks will be given only if there is proper explanation for your Answers)

Image text
(ii) A Master-slave D flip-flop is constructed using two positive D latches as shown in the figure below. The D-to-Q delay (i.e. when the latch is enabled the time taken for output of latch to change after input changes) is 4 n s . The minimum propagation delay and the maximum propagation delay of inverter are given as 1 n s and 2 n s respectively. Determine t setup , t hold , t Clk-Qmin and t Clk-Qmax for the D flip-flop. Give proper justification* for your answers. [ 10 ] ( ∗ Full marks will be given only if there is proper explanation for your Answers)

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Problem 3: (Short Circuit Power Consumption) For the circuit in Figure 2, assume that the input Vin is a periodic square wave signal (called "clock") of frequency 200 MHz, and has a rising transition time (from 0−100% of VDD ) of 0.2 ns and a falling transition time (from 100−0% of VDD ) of 0.2 ns. For the inverter in the figure, find the short circuit power consumption. Use the procedural hints listed below. Procedural Hints:Calculate the short circuit duration, tsc. Short circuit currents occur when both nMOS and pMOS transistors are simultaneously ON. Use the rise/fall times given. Calculate the peak short circuit currents. For simplicity assume that Ipeak_sc_LH and Ipeak_sc_HL are equal, and calculate the latter only. To calculate Ipeak_sc_HL, , assume that the short circuit current for the H-to-L transition peaks when Vin = VDD/2 and Vout = 9 VDD /10 (this is an arbitrary choice assumed for this problem alone). Now calculate the pMOS transistor current - this will be Ipeak_sc_HL. . Question: Does the nMOS current equal the pMOS current? If not, how do you account for InMOS−IpMO ? Using your results from (1) and (2), calculate the short circuit power dissipation. Note: Assume that VDD = 1.0 Volts, (W/L)p = 3.5 /0.1, and (W/L)n = 2 /0.1. Transistor properties are given by the 90 nm model parameters handout posted on the class web-site. For the current calculation, use the transistor parameters (not the equivalent resistance parameters) and ignore channel length modulation. Assume that there is an 89 fF load on Out.

Solution
0 0

For the following figure, all the D flip-flops have setup time as 2 ns, hold time as 4 ns, tclk-a-min = 9 ns and tclk-q-m-max = 11 ns. a) Assuming clock period as 25 ns, determine (by using setup equation) if the circuit has setup violation. If there is set up violation, what should be the value of clock period to avoid setup violation. b) Determine (by using hold time equation), if the circuit has hold time violation. [4] c) Modify (and redraw) the circuit without removing any buffers, such that it works at clock period of 25 ns and does not have any timing violations. (Assume only two buffers, with min delay of 6 ns and max delay of 8 ns, are available). Show clear steps/methodology used for arriving at the violation free circuit. [12]
Solution
0 0

Task 4 Digital Circuits Fig. 4.1 Fig. 4.2 Given are the CMOS gates according to Fig. 4.1 und Fig. 4.2. a) For the gate from Fig. 4.1 determine the output logic values of Y for all possible input logic values A, B, and C and enter them into a truth table. For some logic states you will not be able to determine the output logic value. Denote these states with Y = Z and explain why a definite value for Y cannot be given. b) Now consider the circuit in Fig. 4.2. Determine the output logic values of Y for all possible input logic values A, B, C, and D and enter them into a truth table. c) Draw the circuit diagram of a level-sensitive D-latch and an edge-triggered master-slave Dflipflop. Given is a sequential circuit according to Fig. 4.3. The edge-triggered registers exhibit the following specifications: setup-time tsetup = 200 ps, hold-time thold = 100 ps, propagation delay tpcq = 50 ps, and contamination delay tccq = 50 ps. The maximum clock frequency is 1 GHz. Fig. 4.3 d) Determine the minimal contamination delay tcd for the combinational logic. e) Determine the maximum propagation delay tpd for the combinational logic.
Solution
0 0